Four layers

board "12-four-layers"

# Two pixels, four layers and two internal planes.
# Pixel DOUT is Passive. DIN thresholds and leakage cover only 5 V and 25 C.
# These planes do not establish data transfer across the operating range.
part U1 = catalog C310413 as "L7805"
part C1 = cap 1uF 50V
part C2 = cap 1uF 50V
# Retain lesson 02's minimum load when every pixel is off.
part R1 = res 470R as "minimum load" lcsc C844786
part D[1..2] = catalog C2761795 as "WS2812B"
part G1 = ground as "GND" lcsc C0
part J1 = pin_header rows 1 positions 3 pitch 2.54mm labels "VIN" "GND" "DIN" as "host"

net VIN  { U1.INPUT, C1.1, J1.VIN }
net GND  { U1.GND, C1.2, C2.2, R1.2, G1.P, J1.GND, D1.VSS, D2.VSS }
net VLED { U1.OUTPUT, C2.1, R1.1, D1.VDD, D2.VDD }
net DIN  { J1.DIN, D1.DIN }
net DAT12 { D1.DOUT, D2.DIN }

# Stopgap until supply contacts are derived: VIN sits above the regulator's
# input with both pixels white. A host drives DIN with at most 1 mA; the pixel
# prints 1 uA at 25 C only. GND returns their sum.
interface J1 contacts "VIN" each current max 100mA
interface J1 contacts "DIN" each current max 1mA
interface J1 contacts "GND" each current max 101mA

rail "VIN" 8V
power J1.VIN from "VIN"

ambient 0C..70C

layers 4

# Construction premise: 2s2p requires four layers and two internal planes.
# Thermal equivalence still needs supported fixture and dissipation evidence.
thermal fixture jedec 2s2p

outline fit

emit vocab 1 producer 2 -> "12-four-layers.json"

layout
netclass power nets { VIN VLED } width 0.5mm
route netclass power
route remaining
# Pour both internal planes; check the ground coverage after routing.
plane net GND on In1.Cu
plane net VLED on In2.Cu
assert copper net GND on In1.Cu >= 70%
finish connectivity
finish drc

Source saved with this render · 17 Oct 2026