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Part arrays
Pixel array
Four WS2812B parts expand from one array declaration. The source wires D1 through D4 into a data cascade, with an L7805 supplying the pixel rail.
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board "05-arrays-placement"
# Four catalog pixels powered by a 5 V regulator.
# The card bounds supply draw; DOUT is Passive with no drive guarantee.
# DIN thresholds and leakage are characterized only at 5 V and 25 C.
# Data transfer across this board's operating range remains unproved.
part U1 = catalog C310413 as "L7805"
part C1 = cap 1uF 50V
part C2 = cap 1uF 50V
# Retain lesson 02's minimum load when every pixel is off.
part R1 = res 470R as "minimum load" lcsc C844786
# The array expands to D1-D4; wire each instance by name.
part D[1..4] = catalog C2761795 as "WS2812B"
part GND = ground as "GND" lcsc C0
part J1 = pin_header rows 1 positions 3 pitch 2.54mm as "host"
net VIN { U1.INPUT, C1.1, J1.1 }
net GND { U1.GND, C1.2, C2.2, R1.2, GND.P, J1.2, D1.VSS, D2.VSS, D3.VSS, D4.VSS }
net VLED { U1.OUTPUT, C2.1, R1.1, D1.VDD, D2.VDD, D3.VDD, D4.VDD }
net DIN { J1.3, D1.DIN }
# Connect each DOUT to the next DIN.
net DAT12 { D1.DOUT, D2.DIN }
net DAT23 { D2.DOUT, D3.DIN }
net DAT34 { D3.DOUT, D4.DIN }
# Stopgap until supply contacts are derived: pin 1 sits above the regulator's
# input with every pixel white. A host drives pin 3 with at most 1 mA; the
# pixel prints 1 uA at 25 C only. Pin 2 returns their sum.
interface J1 contacts "1" each current max 175mA
interface J1 contacts "3" each current max 1mA
interface J1 contacts "2" each current max 176mA
rail "VIN" 8V
power J1.1 from "VIN"
# Rated to 60 C: with all four pixels lit the regulator drops about 3 V into
# the 1s0p fixture below, and at 70 C its junction bound passes 125 C.
ambient 0C..60C
# Authored thermal construction premise; qualify it against sourced data.
thermal fixture jedec 1s0p
# Let placement determine size. Add relations for external requirements.
outline fit corner 1.5mm
text "WS2812B x4 CHAIN" 1.0mm at tl 0mm -2.2mm
emit vocab 1 producer 2 -> "05-arrays-placement.json"
layout
# Size the supply routes for the full bounded pixel load.
netclass power nets { VIN, VLED } width 0.5mm
route netclass power
route remaining
finish connectivity
finish drc
Source saved with this render · 17 Oct 2026